Wireless RF PHY FW Engineer

/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. In this highly...

Lugar: San Francisco, CA | 24/10/2025 20:10:09 PM | Salario: S/. $126800 - 190900 per year | Empresa: Apple

Wireless Design Verification Engineer

team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration... for hundreds of millions of customers. As a Wireless Design Verification Engineer, you will be responsible for pre-silicon RTL...

Lugar: San Francisco, CA | 24/10/2025 19:10:40 PM | Salario: S/. $126800 - 190900 per year | Empresa: Apple

Physical Design Engineer

. Description As a Physical Design engineer you will contribute to all phases of physical design of high performance PHY design from RTL...

Lugar: Cupertino, CA | 21/10/2025 20:10:05 PM | Salario: S/. $126800 - 190900 per year | Empresa: Apple

SoC Integration Engineer

of Experience Preferred Qualifications Deep experience in RTL Logic Design of multi-million gate ASICs. Hands on experience...

Lugar: Cupertino, CA | 16/10/2025 22:10:04 PM | Salario: S/. $126800 - 190900 per year | Empresa: Apple

ASIC Design Engineer - Cache Controller

trade-offs in system performance, area, and power consumption. Develop and debug register-transfer level (RTL) design... subsystem Academic experience with RTL/micro-architecture development Good understanding of PPA (performance/power/area...

Lugar: Santa Clara, CA | 10/10/2025 02:10:56 AM | Salario: S/. $126800 - 190900 per year | Empresa: Apple

SOC Verification Engineer

team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration... for pre-silicon RTL verification of block and top level SOC. With deep understanding of SOC architecture and meticulous...

Lugar: San Francisco, CA | 23/09/2025 18:09:31 PM | Salario: S/. $126800 - 190900 per year | Empresa: Apple

CPU Top-Level Design Verification Engineer

power processor design, you will have the responsibilities as follows: • Work closely with verification engineers and RTL... - Strong understanding of processor design, instruction set architectures, pipeline design, cache hierarchies, and memory systems RTL...

Lugar: Santa Clara, CA | 18/09/2025 00:09:38 AM | Salario: S/. $126800 - 190900 per year | Empresa: Apple

CPU Processor Performance Verification Engineer

with architects and RTL designers on verifying the performance features of the design and correlating with performance models... and correlate the RTL and performance model • Develop C or Verilog-based checkers for verifying the performance features • Develop...

Lugar: Santa Clara, CA | 17/09/2025 23:09:38 PM | Salario: S/. $126800 - 190900 per year | Empresa: Apple