Architecture Energy Modeling Engineer - New College Grad 2026

become more energy efficient;and is responsible for building energy models that integrate into architectural simulators, RTL simulation... tools to debug energy inefficiencies observed in various workloads run on silicon, RTL, and architectural simulators...

Lugar: Santa Clara, CA | 28/02/2026 22:02:24 PM | Salario: S/. $116000 - 189750 per year | Empresa: Nvidia

ASIC Hardware Design Engineer - New College Grad 2026

, developing, and delivering system-level methodologies and RTL to measure performance on the industry's leading GPUs and SOCs.... Learn and run RTL checks to ensure design quality (e.g., cross clock domains (CDC), clocks, reset, latency...

Lugar: Austin, TX | 24/01/2026 19:01:25 PM | Salario: S/. $116000 - 189750 per year | Empresa: Nvidia

Staff DFT Engineer

from RTL/netlist through post-silicon debug. In this role, you will partner closely with RTL, Physical Design, and ATE teams... violations at both block and top levels Run, analyze, and debug SpyGlass DFT/RTL checks, working with design teams to close...

Lugar: Santa Clara, CA | 25/02/2026 00:02:36 AM | Salario: S/. $128000 - 189370 per year | Empresa: Marvell

Staff Logic Design Engineer

to reproduce any failures found in the field Fix the RTL, recompile the FPGA and review the changes with the team Requirements... and RTL simulation Strong interpersonal, organizational and communication skills Experience at working both independently...

Lugar: Milpitas, CA | 23/01/2026 00:01:29 AM | Salario: S/. $141900 - 189200 per year | Empresa: Teledyne Technologies

Principal FPGA Engineer I

and route and timing closure) and verification. Proficient in HDL coder, Modelsim RTL simulation tools, Xilinx and Microsemi...

Lugar: Westminster, CO | 16/01/2026 03:01:27 AM | Salario: S/. $158000 - 189000 per year | Empresa: CesiumAstro

Project Design Lead (EX)

RTL code quality and coverage metrics. Collaborate with cross-functional teams including analog designers, system..., to debug design issues in RTL and analyze RTL code coverage;Experience working in at least one project in verification...

Lugar: San Jose, CA | 12/03/2026 02:03:49 AM | Salario: S/. $188760 per year | Empresa: Nexperia

ASIC Verification Engineer

environment for block-level verification, and reusing those environments at subsystem level. Ability to read and understand RTL...

Lugar: Seattle, WA | 26/02/2026 21:02:55 PM | Salario: S/. $76200 - 187740 per year | Empresa: Capgemini

FPGA Engineer III

environment, we want you on our team. Key Responsibilities: Design and implement advanced FPGA modules, including RTL coding... Engineering, or a related technical field. 4–6 years of industry experience in FPGA development, including RTL coding in System...

Lugar: Spokane, WA | 31/01/2026 18:01:52 PM | Salario: S/. $124800 - 187200 per year | Empresa: F5