you because you have been in the trenches with RTL synthesis, FPGA bring-up, and SoC validation. You know what a real prototype timeline looks... in emulation, FPGA-based prototyping, ASIC design, or SoC validation, with deep understanding of RTL-to-hardware workflows...
. Work across the full RTL-to-GDS flow, from implementation through signoff and tapeout readiness. The Impact..., implementation, or CAD engineering experience. Direct experience with RTL-to-GDS implementation flows, including synthesis, place...
is what saves the project. You understand the fundamentals of RTL, testbenches, and verification flows, but you are ready... through RTL code, testbenches, emulation tool configurations, and hardware logs to isolate root causes Support presales...
, and translating that into a working ProtoCompiler flow. When something breaks, you can work through logs, timing reports, and RTL..., ProtoCompiler runtime debug tools, and protocol analyzers to troubleshoot RTL, netlist, timing, and hardware issues The Impact...
Date posted 09/13/2026 Share this job Position Summary The Staff Applications Engineer for Prime Power RTL 2.0 independently... supports and leads customer deployments of RTL-stage power analysis, estimation, and optimization. This role owns end-to-end...
Debug complex physical design issues across the RTL-to-GDS flow, including placement, CTS, routing, timing closure... experience with RTL-to-GDS flows using industry-standard tools, including placement, optimization, clock tree synthesis...
to join our Physical Design organization. In this role, you will be responsible for implementing custom IP and SoC designs from RTL through... products. You will collaborate closely with RTL designers, Design Verification, DFT, Timing, and CAD teams to deliver high...
from RTL through GDSII while driving timing closure, power optimization, physical verification, and design signoff for leading...-edge semiconductor products. You will work closely with architecture, RTL, DFT, synthesis, verification, and methodology...
at our Altera Headquarters in San Jose, CA. In this specialized role, you will be responsible for the micro-architecture, RTL design... Responsibilities FPGA-Targeted RTL Design: Micro-architect, design, and implement Soft CPU cores (using SystemVerilog/Verilog...
of technology. Opportunity Overview Teradyne's Digital ASIC Group is seeking a Senior RTL Digital Design Engineer to help... required;MSEE or PhD desired. 8+ years of ASIC or digital design experience with strong expertise in Verilog/SystemVerilog RTL...