corrective measures to resolve failing tests. Collaborates with GPU architects, RTL developers, and physical design teams...: Experience with RTL design verification using SystemVerilog/UVM Experience with C/C++/Python Requirements listed...
Lugar:
Hillsboro, OR | 06/03/2026 01:03:57 AM | Salario: S/. $105650 - 172860 per year | Empresa:
Intel architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural...
Lugar:
Austin, TX | 21/02/2026 18:02:45 PM | Salario: S/. $91150 - 172860 per year | Empresa:
Intel of implementation and supporting RTL designs using Verilog/SystemVerilog. Responsibilities include, but are not limited to the... and documentation. High-quality, high-performance Verilog/SystemVerilog RTL implementation based on a design specification – may...
RTL Synthesis IC Design Engineer Broadcom is searching for a RTL Synthesis IC Design Engineer to join the Data Center... in-depth knowledge and expertise in front-end synthesis towards taking RTL to silicon tape-out. Responsibilities include...
on design / Si debug. BSEE and 8+ years of industry experience in RTL design is a must, or MSEE and 6+ years of industry...
Lugar:
Irvine, CA | 03/03/2026 18:03:44 PM | Salario: S/. $108000 - 172800 per year | Empresa:
Broadcom simulations of the transceiver and perform vector matching verification with RTL simulations Lab testing and debug of ASICs... based products is highly desirable Good hands-on skills in the lab RTL coding expertise is a plus Good oral...
Lugar:
Irvine, CA | 18/02/2026 19:02:56 PM | Salario: S/. $108000 - 172800 per year | Empresa:
Broadcom for verifications of RTL and gatesim-based designs at both the block and chip level. The engineer will also be tasked with creating...
Lugar:
San Jose, CA | 03/02/2026 22:02:48 PM | Salario: S/. $108000 - 172800 per year | Empresa:
Broadcom. Proven experience in RTL lint checking, scan compression, scan insertion, and the ATPG process. Experience in MBIST...
Lugar:
USA | 17/01/2026 03:01:52 AM | Salario: S/. $108000 - 172800 per year | Empresa:
Broadcom Responsibilities FPGA & Zynq Development Design and implement FPGA logic using Vivado, IP Integrator, and Vitis. Develop RTL...
, you will develop RTL/HDL for devices that make electric power safter, more reliable, and more economical. You will work with firmware... acquisition, digital signal processing, and communication protocol RTL sub-systems Modeling low-level and system-level designs...