Physical IC Design Engineer

Design aspects of taking RTL to silicon tape-out. Responsibilities include, but are not limited to the following...: Execution of Physical Design, Synthesis, Physical Verification, and Timing Closure Setup and Synthesizing RTL Timing closure...

Lugar: San Jose, CA | 10/12/2025 23:12:44 PM | Salario: S/. $120000 - 192000 per year | Empresa: Broadcom

Physical IC Design Engineer

Design aspects of taking RTL to silicon tape-out. Responsibilities include, but are not limited to the following...: Execution of Physical Design, Synthesis, Physical Verification, and Timing Closure Setup and Synthesizing RTL Timing closure...

Lugar: San Jose, CA | 10/12/2025 19:12:19 PM | Salario: S/. $120000 - 192000 per year | Empresa: Broadcom

Physical IC Design Engineer

Design aspects of taking RTL to silicon tape-out. Responsibilities include, but are not limited to the following...: Execution of Physical Design, Synthesis, Physical Verification, and Timing Closure Setup and Synthesizing RTL Timing closure...

Lugar: San Jose, CA | 10/12/2025 19:12:08 PM | Salario: S/. $120000 - 192000 per year | Empresa: Broadcom

Physical Design Engineer

experience - Work closely with RTL & DFT designers - Strong TCL/Python scripting knowledge required, Perl is a plus. - Good...

Lugar: San Jose, CA | 20/11/2025 02:11:59 AM | Salario: S/. $120000 - 192000 per year | Empresa: Broadcom

Chip Integration Engineer

successful candidate will be responsible for various key tasks in the areas of chip integration and RTL design of cutting-edge network.... 5). Develop Verilog RTL. design verification support, logic synthesis, physical implementation constraints, static...

Lugar: San Jose, CA | 19/11/2025 18:11:22 PM | Salario: S/. $120000 - 192000 per year | Empresa: Broadcom

Verification Engineer

of industry standard verification methodologies and tools Hands on and In-depth knowledge in UVM, System Verilog, RTL design...

Lugar: San Jose, CA | 30/10/2025 18:10:13 PM | Salario: S/. $120000 - 192000 per year | Empresa: Broadcom

High Speed Serdes System Design Engineer

with RTL simulations Develop, test, and debug firmware associated with physical layer functionality Lab testing and debug... in equalization techniques for wireline communication applications such as read-channel is also a very big plus. RTL coding...

Lugar: USA | 16/01/2026 18:01:42 PM | Salario: S/. $108000 - 192000 per year | Empresa: Broadcom

Lead Application Engineer

, Engineering, or related field Strong RTL and Testbench debug skills Experience in synthesizable coding style Experience... from RTL to bitstream for Xilinx and/or Altera products Hands on experience with lab bring up, debug, chipscope and instrument...

Lugar: San Jose, CA | 04/12/2025 18:12:26 PM | Salario: S/. $102900 - 191100 per year | Empresa: Cadence Design Systems

Integration Engineer

. • RTL Integration: Manage and merge RTL codebases, ensure connectivity and bus/interface protocols (e.g., AMBA, AXI, AHB...) are correctly implemented. • Top-Level Assembly: Create and maintain top-level SoC RTL, wrappers, and interconnects. • Linting...

Lugar: Santa Clara, CA | 07/11/2025 01:11:29 AM | Salario: S/. $126800 - 190900 per year | Empresa: Apple