successful candidate will be responsible for various key tasks in the areas of chip integration and RTL design of cutting-edge network.... 5). Develop Verilog RTL. design verification support, logic synthesis, physical implementation constraints, static...
Lugar:
San Jose, CA | 20/11/2025 03:11:58 AM | Salario: S/. $120000 - 192000 per year | Empresa:
Broadcom experience - Work closely with RTL & DFT designers - Strong TCL/Python scripting knowledge required, Perl is a plus. - Good...
Lugar:
San Jose, CA | 20/11/2025 02:11:53 AM | Salario: S/. $120000 - 192000 per year | Empresa:
Broadcom of industry standard verification methodologies and tools Hands on and In-depth knowledge in UVM, System Verilog, RTL design...
Lugar:
San Jose, CA | 30/10/2025 19:10:24 PM | Salario: S/. $120000 - 192000 per year | Empresa:
Broadcom) Strong understanding of ASIC design flows, including RTL and place-and-route. Excellent problem-solving skills and attention to detail...
Lugar:
San Jose, CA | 10/10/2025 01:10:33 AM | Salario: S/. $120000 - 192000 per year | Empresa:
Broadcom, Engineering, or related field Strong RTL and Testbench debug skills Experience in synthesizable coding style Experience... from RTL to bitstream for Xilinx and/or Altera products Hands on experience with lab bring up, debug, chipscope...
, Engineering, or related field Strong RTL and Testbench debug skills Experience in synthesizable coding style Experience... from RTL to bitstream for Xilinx and/or Altera products Hands on experience with lab bring up, debug, chipscope and instrument...
and synthesis tools · Strong knowledge of ASIC flow, RTL/Verilog · Individual leadership and initiative to manage pre-sales...
team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration.../C system model RTL logic design and verification support Running tools to ensure lint-free design Collaboration...
Lugar:
Sunnyvale, CA | 24/10/2025 23:10:22 PM | Salario: S/. $126800 - 190900 per year | Empresa:
Apple drive CPU multi-level cache subsystem architecture and RTL development for multi-processor systems. Description As a CPU... Microarchitect/RTL Engineer, you will participate in the following: • Micro-architecture development and specification - from early...
Lugar:
Santa Clara, CA | 16/10/2025 18:10:32 PM | Salario: S/. $126800 - 190900 per year | Empresa:
Apple. • RTL Integration: Manage and merge RTL codebases, ensure connectivity and bus/interface protocols (e.g., AMBA, AXI, AHB...) are correctly implemented. • Top-Level Assembly: Create and maintain top-level SoC RTL, wrappers, and interconnects. • Linting...
Lugar:
Santa Clara, CA | 06/11/2025 19:11:50 PM | Salario: S/. $126800 - 190900 per year | Empresa:
Apple