communication chip architecture and RTL design or MSEE and 6+ years of industry experience. Strong knowledge & background... definition, RTL coding, simulation/verification, synthesis, timing closure, and silicon validation are required. Must have strong...
Lugar:
Irvine, CA | 13/10/2026 19:10:02 PM | Salario: S/. $121900 - 195000 per year | Empresa:
Broadcom, this position will require in-depth knowledge and expertise in all Physical Design aspects of taking RTL to silicon tape-out..., and Timing Closure Setup and Synthesizing RTL Timing closure through various methods and strategies;preferable in-depth...
Design aspects of taking RTL to silicon tape-out. Responsibilities include, but are not limited to the following...: Execution of Physical Design, Synthesis, Physical Verification, and Timing Closure Setup and Synthesizing RTL Timing closure...
with RTL simulations Develop, test, and debug firmware associated with physical layer functionality Lab testing and debug... in equalization techniques for wireline communication applications such as read-channel is also a very big plus. RTL coding...
Lugar:
USA | 02/09/2026 23:09:26 PM | Salario: S/. $121900 - 195000 per year | Empresa:
Broadcom strong coding and debugging experience in C/C++. Must have experience with pre-silicon/RTL and SW co-simulation environment...
and experience with RTL Synthesis design flows and verification tools is recommended. Must have strong scripting skills with tcl..., perl, and other scripting languages. Technical writing skills are highly recommended. Having experience in RTL coding...
and/or features The ideal candidate would have: 2+ year experience in FPGA or ASIC design from RTL/HDL through simulation...
Lugar:
San Diego, CA | 28/10/2026 01:10:32 AM | Salario: S/. $129500 - 194300 per year | Empresa:
Qualcomm in Costa Mesa, CA. In this role, you will design and integrate RTL for FPGA and SoC platforms used in high-performance embedded... and microarchitecture through RTL implementation, simulation, synthesis, timing closure, lab bring-up, and system integration...
and system level Collaborate with design engineers on RTL reviews, bug resolution, and micro-architecture refinement Support...
ingenuity of tomorrow. You Are You have spent years in the trenches of ASIC design, and you know that the cleanest RTL... everything, and what you recommend will show up in silicon. What You'll Be Doing Own technical relationships with customer RTL, synthesis, formal...
Lugar:
Sunnyvale, CA | 24/10/2026 01:10:18 AM | Salario: S/. $129000 - 193000 per year | Empresa:
Synopsys