GPU Design Engineer - Memory Hierarchy
! Description As a GPU Design Engineer, you will participate in micro-architecture specification and RTL coding. Explore architecture trade...
! Description As a GPU Design Engineer, you will participate in micro-architecture specification and RTL coding. Explore architecture trade...
's state-of-the-art Hexagon NPU, powering a wide range of AI/ML applications. In addition to microarchitecture and RTL... and develop microarchitecture for future generations of Qualcomm's Hexagon NPU. Drive RTL design in SystemVerilog, owning...
of the ASIC design flow from RTL to GDS2 and the challenges posed by advanced technologies. The successful candidate... will possess detailed understanding of RTL design, synthesis, static timing analysis, PLDRC, clock domain crossing, and low power...
design. Familiarity with the semiconductor manufacturing flow (fab, assembly, test) and IC design cycles (RTL to GDSII flow...
will have: *RTL Design *ASIC front-end experience *Scripting Languages knowledge (e.g. Perl or Python) Minimum Qualifications...
into implementable DSP blocks for ASIC design, collaborating with RTL and physical design teams to define fixed-point accuracy... algorithms - RTL handoff, verification, and bit-accurate modelling. Experience in lab-based silicon bring-up, calibration...
into implementable DSP blocks for ASIC design, collaborating with RTL and physical design teams to define fixed-point accuracy... algorithms — RTL handoff, verification, and bit-accurate modelling. Experience in lab-based silicon bring-up, calibration...
mining analysis at the RTL and gate-level to define relevant micro-architectural transactions for high-level power estimation...
, micro-architecture, RTL Design, methodology and AI based power optimization solutions. You will collaborate with Architects... standard pre-silicon gate-level and RTL power analysis tools, to help improve product power efficiency. Use artificial...
) improvements. Execute and deliver fully verified, high performance, area and power efficient RTL to achieve design targets...