ASIC Design Engineer

with: - Architecture research and/or development of memory or highly interconnected system architectures. - RTL/micro-architecture...

Lugar: Santa Clara, CA | 30/10/2025 18:10:49 PM | Salario: S/. $126800 - 190900 per year | Empresa: Apple

Wireless SOC FW Engineer

team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration...

Lugar: San Francisco, CA | 29/10/2025 03:10:37 AM | Salario: S/. $126800 - 190900 per year | Empresa: Apple

CPU DFT Verification Engineer

. Description As a CPU DFT Verification Engineer, you will have the following responsibilities: • Work closely with architecture, RTL...

Lugar: Santa Clara, CA | 28/10/2025 23:10:13 PM | Salario: S/. $126800 - 190900 per year | Empresa: Apple

Firmware Validation Engineer

team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration...

Lugar: San Francisco, CA | 28/10/2025 22:10:46 PM | Salario: S/. $126800 - 190900 per year | Empresa: Apple

CPU Design Verification Engineer

responsibilities as follows: • Work closely with architecture and RTL designers on verifying the functionality correctness of the...

Lugar: Santa Clara, CA | 28/10/2025 22:10:24 PM | Salario: S/. $126800 - 190900 per year | Empresa: Apple

Firmware Validation Engineer

team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration...

Lugar: San Francisco, CA | 25/10/2025 22:10:13 PM | Salario: S/. $126800 - 190900 per year | Empresa: Apple

PHY Design Verification Engineer

team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration... for hundreds of millions of customers. As a PHY Design Verification Engineer, you will be responsible for pre-silicon RTL...

Lugar: San Francisco, CA | 25/10/2025 00:10:40 AM | Salario: S/. $126800 - 190900 per year | Empresa: Apple