Lead IC Emulation Verification AE

Strong RTL and Testbench debug skills Experience in synthesizable coding style Experience in writing scripts (Perl, Python... with multiple clock domains and asynchronous interfaces Knowledge of the FPGA development process & tool flow from RTL to bitstream...

Lugar: San Jose, CA | 05/12/2025 01:12:01 AM | Salario: S/. $102900 - 191100 per year | Empresa: Cadence Design Systems

Integration Engineer

. • RTL Integration: Manage and merge RTL codebases, ensure connectivity and bus/interface protocols (e.g., AMBA, AXI, AHB...) are correctly implemented. • Top-Level Assembly: Create and maintain top-level SoC RTL, wrappers, and interconnects. • Linting...

Lugar: Santa Clara, CA | 06/11/2025 20:11:52 PM | Salario: S/. $126800 - 190900 per year | Empresa: Apple

AI/ML RTL Engineer

's state-of-the-art Hexagon NPU, powering a wide range of AI/ML applications. In addition to microarchitecture and RTL... and develop microarchitecture for future generations of Qualcomm's Hexagon NPU. Drive RTL design in SystemVerilog, owning...

Lugar: Austin, TX | 29/01/2026 00:01:28 AM | Salario: S/. $127200 - 190800 per year | Empresa: Qualcomm

Processor ASIC RTL Design Engineer

of the ASIC design flow from RTL to GDS2 and the challenges posed by advanced technologies. The successful candidate... will possess detailed understanding of RTL design, synthesis, static timing analysis, PLDRC, clock domain crossing, and low power...

Lugar: San Diego, CA | 23/01/2026 22:01:00 PM | Salario: S/. $127200 - 190800 per year | Empresa: Qualcomm

Power Electronics Research Engineer

design. Familiarity with the semiconductor manufacturing flow (fab, assembly, test) and IC design cycles (RTL to GDSII flow...

Lugar: Dearborn, MI | 18/01/2026 01:01:17 AM | Salario: S/. $113580 - 190500 per year | Empresa: Ford

(Senior) Engineer, DSP Systems Engineering, meoSphere

into implementable DSP blocks for ASIC design, collaborating with RTL and physical design teams to define fixed-point accuracy... algorithms - RTL handoff, verification, and bit-accurate modelling. Experience in lab-based silicon bring-up, calibration...

Lugar: Long Beach, CA | 20/12/2025 02:12:07 AM | Salario: S/. $150000 - 190000 per year | Empresa: SES S.A.

(Senior) Engineer, DSP Systems Engineering, meoSphere

into implementable DSP blocks for ASIC design, collaborating with RTL and physical design teams to define fixed-point accuracy... algorithms — RTL handoff, verification, and bit-accurate modelling. Experience in lab-based silicon bring-up, calibration...

Lugar: Long Beach, CA | 19/12/2025 18:12:36 PM | Salario: S/. $150000 - 190000 per year | Empresa: SES

ASIC Design Efficiency Engineer

) improvements. Execute and deliver fully verified, high performance, area and power efficient RTL to achieve design targets...

Lugar: Santa Clara, CA | 29/01/2026 21:01:26 PM | Salario: S/. $116000 - 189750 per year | Empresa: Nvidia