AI/ML RTL Engineer

's state-of-the-art Hexagon NPU, powering a wide range of AI/ML applications. In addition to microarchitecture and RTL... and develop microarchitecture for future generations of Qualcomm's Hexagon NPU. Drive RTL design in SystemVerilog, owning...

Lugar: Austin, TX | 28/01/2026 21:01:28 PM | Salario: S/. $127200 - 190800 per year | Empresa: Qualcomm

Processor ASIC RTL Design Engineer

of the ASIC design flow from RTL to GDS2 and the challenges posed by advanced technologies. The successful candidate... will possess detailed understanding of RTL design, synthesis, static timing analysis, PLDRC, clock domain crossing, and low power...

Lugar: San Diego, CA | 23/01/2026 23:01:33 PM | Salario: S/. $127200 - 190800 per year | Empresa: Qualcomm

Power Electronics Research Engineer

design. Familiarity with the semiconductor manufacturing flow (fab, assembly, test) and IC design cycles (RTL to GDSII flow...

Lugar: Dearborn, MI | 17/01/2026 23:01:14 PM | Salario: S/. $113580 - 190500 per year | Empresa: Ford

Senior ASIC Engineer

will have: *RTL Design *ASIC front-end experience *Scripting Languages knowledge (e.g. Perl or Python) Minimum Qualifications...

Lugar: Santa Clara, CA | 01/11/2025 18:11:00 PM | Salario: S/. $126700 - 190100 per year | Empresa: Qualcomm

(Senior) Engineer, DSP Systems Engineering, meoSphere

into implementable DSP blocks for ASIC design, collaborating with RTL and physical design teams to define fixed-point accuracy... algorithms - RTL handoff, verification, and bit-accurate modelling. Experience in lab-based silicon bring-up, calibration...

Lugar: Long Beach, CA | 20/12/2025 03:12:35 AM | Salario: S/. $150000 - 190000 per year | Empresa: SES S.A.

(Senior) Engineer, DSP Systems Engineering, meoSphere

into implementable DSP blocks for ASIC design, collaborating with RTL and physical design teams to define fixed-point accuracy... algorithms — RTL handoff, verification, and bit-accurate modelling. Experience in lab-based silicon bring-up, calibration...

Lugar: Long Beach, CA | 19/12/2025 18:12:50 PM | Salario: S/. $150000 - 190000 per year | Empresa: SES

ASIC Design Efficiency Engineer

) improvements. Execute and deliver fully verified, high performance, area and power efficient RTL to achieve design targets...

Lugar: Santa Clara, CA | 30/01/2026 00:01:59 AM | Salario: S/. $116000 - 189750 per year | Empresa: Nvidia