Design Verification Engineer

of a verification team responsible for the full cycle of RTL verification for FPGA and ASIC designs. Over the span of a project, you may...

Lugar: Boston, MA | 30/10/2024 23:10:29 PM | Salario: S/. $99800 - 173400 per year | Empresa: Viasat

VP, Publishing (US & Latin)

by international media, services and education company Bertelsmann, whose other content businesses include the broadcaster RTL Group...

Lugar: Los Angeles, CA | 05/12/2024 03:12:23 AM | Salario: S/. $150000 - 173000 per year | Empresa: RTL

IC Verification Engineer

analysis, and functional verification. Perform RTL code coverage, assertion coverage, and gate level simulations. Drive...

Lugar: USA | 16/01/2025 22:01:42 PM | Salario: S/. $107000 - 171000 per year | Empresa: Broadcom

IP Integration Lead Engineer

ASIC design flow including FET design, RTL, synthesis, timing, floorplanning, power planning, P&R, LVS, DRC... Experience or coursework with RTL languages(i.e SystemVerilog, Verilog, VHDL) Experience scripting in Skill, TCL, Ruby, Bash...

Lugar: Fort Collins, CO | 03/12/2024 19:12:41 PM | Salario: S/. $107000 - 171000 per year | Empresa: Broadcom