, Intel or Microsemi FPGA devices and their associated application environments Experience writing custom FPGA RTL using... experience using Vivado XSIM or a similar tool Experience integrating FPGA IP with custom RTL is a plus Experience integrating...
. You are comfortable translating RTL-level complexity into business value that resonates with a program manager, and you can flip back... with their existing RTL-to-hardware workflows Conduct technical evaluations, proof-of-concept projects, and benchmarks that demonstrate...
Lugar:
Sunnyvale, CA | 09/10/2026 18:10:28 PM | Salario: S/. $109000 - 163000 per year | Empresa:
Synopsys-$163000 Date posted 09/13/2026 Share this job Position Summary The Senior Applications Engineer for Prime Power RTL... 2.0 supports customer and internal RTL power analysis activities under general supervision. This role executes established PPRTL...
Lugar:
USA | 16/09/2026 22:09:33 PM | Salario: S/. $109000 - 163000 per year | Empresa:
Synopsys Comfortable using ATE, bench, and wafer test systems Additional Qualifications: Understanding of RTL (VHDL or Verilog...
, this position will require in-depth knowledge surrounding all aspects of implementation and supporting RTL designs using Verilog.../SystemVerilog RTL implementation based on a design specification – may also include areas such as asynchronous clock domain...
: Experience working with complex digital designs Experience in different stages of FPGA development: RTL design, verification...
Lugar:
USA | 15/10/2026 17:10:44 PM | Salario: S/. $125000 - 160000 per year | Empresa:
SpaceX+ years of experience in RTL Design using SystemVerilog, Verilog or VHDL PREFERRED SKILLS AND EXPERIENCE: ASIC/FPGA...
Lugar:
USA | 01/10/2026 17:10:48 PM | Salario: S/. $125000 - 160000 per year | Empresa:
SpaceX, develop timing, power and area design targets, and explore RTL/design tradeoffs Resolve design/timing/congestion and flow...
Lugar:
USA | 12/09/2026 17:09:32 PM | Salario: S/. $125000 - 160000 per year | Empresa:
SpaceX, counters, buffers, synchronizers, serializers/de-serializers, etc.;ability to understand RTL and gate-level netlists...
Lugar:
USA | 25/08/2026 17:08:01 PM | Salario: S/. $125000 - 160000 per year | Empresa:
SpaceX. Represent the FPGA team on project core teams and at program reviews. Contribute to FPGA implementation (i.e. code RTL blocks... release. Extensive experience coding RTL (verilog preferred). Extensive experience using digital simulation tools (Cadence...