ASIC Design Engineer - Hardware

, developing, and delivering system-level methodologies and RTL to measure performance on the industry's leading GPUs and SOCs... IP and support projects by applying the performance monitoring system Run and debug RTL checks to ensure design quality...

Lugar: Austin, TX | 17/01/2025 01:01:07 AM | Salario: S/. No Especificado | Empresa: Nvidia

SRAM Circuit Design Engineer

team to create optimal GDS. - Verify extracted GDS meets design specifications. - Backend verification, IR/EM. - Write RTL...

Lugar: Austin, TX | 16/01/2025 23:01:16 PM | Salario: S/. No Especificado | Empresa: Apple

SOC Verification Engineer

team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration..., you will be responsible for pre-silicon RTL verification of block and top-level SOC. With deep understanding of SOC architecture...

Lugar: Sunnyvale, CA | 16/01/2025 23:01:58 PM | Salario: S/. No Especificado | Empresa: Apple

Mgr II- Eng Elec

tradeoffs Experienced in all stages of FPGA and/or ASIC development including requirements management, RTL design, synthesis...

Lugar: Manchester, NH | 16/01/2025 22:01:24 PM | Salario: S/. No Especificado | Empresa: BAE Systems

SOC Verification Engineer

team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration..., you will be responsible for pre-silicon RTL verification of block and top-level SOC. With deep understanding of SOC architecture...

Lugar: Sunnyvale, CA | 16/01/2025 19:01:56 PM | Salario: S/. No Especificado | Empresa: Apple

Silicon Design Engineer

flows Experience with SystemVerilog RTL development Experience with IC packaging, validation and production test... for both internal and customer facing interaction Proficient in debugging firmware and RTL code using simulation tools ACADEMIC...

Lugar: Rochester, NY | 16/01/2025 19:01:57 PM | Salario: S/. No Especificado | Empresa: Advanced Micro Devices

Application Engineer II SCBU

/DSPF, Spice, IC/ASIC design flow knowledge from RTL to GDSII, custom circuit analysis & design, knowledge of low power...

Lugar: Austin, TX | 16/01/2025 18:01:15 PM | Salario: S/. No Especificado | Empresa: Ansys

ASIC Design Engineer, Technical Leader

and participate in micro-architecture specification reviews. Implement Verilog RTL to meet timing and performance requirements. Help... and waveform debug experience. Experience resolving setup and hold timing violations with RTL modification. Experience developing...

Lugar: San Jose, CA | 16/01/2025 18:01:49 PM | Salario: S/. No Especificado | Empresa: Cisco Systems