FPGA / ASIC Design Engineer
peripherals and interrupts Experience deploying designs on FPGA or SDR platforms, from RTL, through simulation, synthesis, lab...
Lugar: Bedford, MA | 03/11/2026 19:11:29 PM | Salario: S/. No Especificado | Empresa: Mitre
Physical Design Engineer
on advanced nodes (7nm, 5nm, 3nm or below) Collaborate with: RTL & Micro architecture teams DFT & Test engineers Foundry...
Lugar: Palo Alto, CA | 03/11/2026 18:11:42 PM | Salario: S/. No Especificado | Empresa: INA Solution Inc
Data Architect - Mortgage & Capital Markets - NYC
-agency/non-QM, RTL/fix-and-flip, securitization and investor reporting. - Working understanding of capital markets concepts...
Lugar: USA | 03/11/2026 18:11:04 PM | Salario: S/. No Especificado | Empresa: Nexiva Inc
Mid-Level Electrical Engineer
development, detailed design, schematic capture, and PCB layout. Experience with FPGA RTL development and simulation is strongly... vias Experience with VHDL for FPGA RTL development Experience with OSVVM and VHDL for FPGA simulation Experience...
Lugar: Raleigh, NC | 03/11/2026 18:11:02 PM | Salario: S/. No Especificado | Empresa: Applied Research Associates
Senior Electrical Engineer
development, detailed design, schematic capture, and PCB layout. Experience with FPGA RTL development and simulation is strongly... vias Experience with VHDL for FPGA RTL development Experience with OSVVM and VHDL for FPGA simulation Experience...
Lugar: Raleigh, NC | 03/11/2026 18:11:44 PM | Salario: S/. No Especificado | Empresa: Applied Research Associates
VLSI Physical Designer
the RTL design into a physical layout of the chip using Synopsys Fusion Compiler synthesis and place-and-route tools. The... Caliber DRC, LVS, antenna and density, especially in the latest nodes such as 5nm and 3nm. RTL to GDSII: Synthesis...
Lugar: USA | 03/11/2026 18:11:12 PM | Salario: S/. No Especificado | Empresa: SoftPathTechnologies
Front End Design Engineer
About the role Remote contract for digital hardware engineers: turn real RTL work into design, bug-fix and PPA (power...
Analog Mixed-Signal SystemVerilog Modeling Engineer
closely with analog circuit designers, RTL designers, and verification engineers. The candidate will be responsible... cause in the model, RTL, or testbench. Documenting model behavior, limitations, and interfaces. EXPERIENCE AND EDUCATION...
Lugar: San Jose, CA | 03/11/2026 18:11:35 PM | Salario: S/. No Especificado | Empresa: Cynet Systems
FPGA Engineer
of 5-7 Years FPGA Engineers having below skills Strong Verilog HDL and RTL design expertise. Good knowledge of CDC...
Lugar: Raleigh, NC | 03/11/2026 18:11:15 PM | Salario: S/. No Especificado | Empresa: Amaze Systems
FPGA Engineer
having below skills Strong Verilog HDL and RTL design expertise. Good knowledge of CDC, reset design, pipelining, FIFO...
Lugar: Raleigh, NC | 03/11/2026 18:11:58 PM | Salario: S/. No Especificado | Empresa: Veridian Tech