FPGA Engineer

and/or ASICs. Experience coding in VHDL, Verilog, SystemVerilog as well as C or C++. Experience with RTL synthesis, writing...

Lugar: Chicago, IL | 11/01/2025 20:01:51 PM | Salario: S/. No Especificado | Empresa: Optiver

High-Level Synthesis Technologist

Algorithm/DSP implementations in HLS or RTL targeting verticals such as wireless, optical communication, image/video processing... Engineering, or Digital Hardware Design with High-Level Synthesis or traditional RTL synthesis Direct hands-on ASIC or FPGA...

Lugar: Wilsonville, OR | 11/01/2025 03:01:50 AM | Salario: S/. No Especificado | Empresa: Siemens

Electrical Engineer, Digital ASIC design

level digital implementation. In this position you will do the following: - Verilog RTL-level digital designs, debug... skills Basic RTL coding and documentation practices Verilog (preferred) or VHDL fluency in design, simulation...

Lugar: Plantation, FL | 10/01/2025 01:01:16 AM | Salario: S/. No Especificado | Empresa: Motorola Solutions