Principal ASIC/SoC Architect & Design Engineer

’s components. RTL Design and Synthesis: - Use Synopsys Design Compiler to create RTL (Register Transfer Level) designs.... - Optimize RTL code for area, power, and performance. - Implement and verify complex digital blocks. Constraint Development...

Lugar: Minneapolis, MN | 01/11/2026 00:11:31 AM | Salario: S/. No Especificado | Empresa: Chelsea Search Group

Senior ASIC Design Engineer - Agentic AI

that will help the ASIC team implement high performance, area and power efficient RTL to achieve design targets and specifications... RTL, and deliver a fully verified, synthesis/timing clean design. Collaborate and coordinate with other designers...

Lugar: Santa Clara, CA | 31/10/2026 23:10:58 PM | Salario: S/. No Especificado | Empresa: Nvidia

ASIC Design Engineer - New College Grad 2026

and deliver high performance, area and power efficient RTL to achieve design targets and specifications. Analyze architectural... trade-offs based on features, performance requirements and system limitations. Craft micro-architecture, implement in RTL...

Lugar: Santa Clara, CA | 31/10/2026 22:10:06 PM | Salario: S/. No Especificado | Empresa: Nvidia

EDA Methodology Architect

, with expertise in key stages such as RTL, DFT, synthesis, placement, optimization, CTS, routing, and signoff. Creativity and self..., RTL, DFT, synthesis, physical design, power, signoff, and CAD/methodology teams as a key technical leader and bridge...

Lugar: Santa Clara, CA | 31/10/2026 21:10:53 PM | Salario: S/. No Especificado | Empresa: Nvidia