CPU Design Verification Engineer

of functionality in a CPU design, you will have the responsibilities as follows: • Work closely with architecture and RTL designers...

Lugar: Beaverton, OR | 21/12/2024 03:12:12 AM | Salario: S/. No Especificado | Empresa: Apple

CPU Design Verification Engineer

of functionality in a CPU design, you will have the responsibilities as follows: • Work closely with architecture and RTL designers...

Lugar: Beaverton, OR | 21/12/2024 00:12:58 AM | Salario: S/. No Especificado | Empresa: Apple

ASIC DESIGN FOR TEST ENGINEER - Acacia

/Fuse. You will work with seasoned DFT engineers to implement and verify DFT. You will also interact with RTL/PD/STA... Prior experience implementing scan control logic in RTL Prior experience with hierarchical ATPG and core wrapping...

Lugar: Maynard, MA | 20/12/2024 18:12:01 PM | Salario: S/. No Especificado | Empresa: Cisco Systems

Senior FPGA Engineer

documents. – Develop RTL designs using SystemVerilog, with emphasis on DSP and digital communication system blocks (frontend... with FPGAs (Xilinx, Altera, etc.). – 8+ years of experience with SystemVerilog, Verilog, or VHDL RTL design. – 3+ years...

Lugar: Linthicum Heights, MD | 20/12/2024 18:12:42 PM | Salario: S/. No Especificado | Empresa: Next Step Systems

ASIC Design Engineer

spec / micro-architecture and RTL development · Design size/timing/power optimization via micro-architecture/RTL...

Lugar: San Jose, CA | 19/12/2024 22:12:36 PM | Salario: S/. No Especificado | Empresa: Infinera

Staff Engineer, ASIC Validation

with scripting languages, preferably Python Basic RTL design & verification skills & proficiency in DSP logic validation and DSP...

Lugar: San Jose, CA | 19/12/2024 18:12:54 PM | Salario: S/. No Especificado | Empresa: Infinera