Principal FPGA Emulation Engineer

with our silicon RTL and DSP architects, you will bring their designs up on FPGA to validate real-time digital, mixed-signal, and power...-control architectures pre-silicon - proving out control loops, catching RTL issues early, and de-risking tape-out. These...

Lugar: Austin, TX | 30/10/2026 18:10:19 PM | Salario: S/. No Especificado | Empresa: Renesas Electronics

Silicon CAD Technical Product Manager

. Design and verification methodologies. RTL quality, lint, clock and reset domain crossing (CDC/RDC), constraints, simulation..., power, equivalence and signoff;front-end/back-end handoffs;early power, performance and area (PPA) estimation and RTL...

Lugar: Austin, TX | 30/10/2026 18:10:13 PM | Salario: S/. No Especificado | Empresa: Ericsson

CAD Design Enablement TPM

. Design and verification methodologies. RTL quality, lint, clock and reset domain crossing (CDC/RDC), constraints, simulation..., power, equivalence and signoff;front-end/back-end handoffs;early power, performance and area (PPA) estimation and RTL...

Lugar: Austin, TX | 30/10/2026 18:10:56 PM | Salario: S/. No Especificado | Empresa: Ericsson

CPU Cores Global Performance Lead

and collaborate with the Core Architecture and RTL teams to make AMD’s ambitious future CPU roadmap a reality. THE PERSON... Cores. Partner with Core Architecture and RTL teams to deliver a high-performance CPU core that meets or exceeds program...

Lugar: Santa Clara, CA | 30/10/2026 01:10:35 AM | Salario: S/. No Especificado | Empresa: Advanced Micro Devices