DFT Application Engineer
Collaborate with RTL and Hard IP designers on DFT/DFM implementation methodology and work with physical designers on DFT/DFM...
Lugar: Chandler, AZ | 10/01/2026 22:01:10 PM | Salario: S/. No Especificado | Empresa: Intel
CPU Physical Design Engineer
implementation of custom CPU designs from RTL to GDS to create a design database that is ready for manufacturing. Conducts...
Lugar: Austin, TX | 10/01/2026 21:01:06 PM | Salario: S/. No Especificado | Empresa: Intel
IP Enablement Application Engineer
in SOC IP Integration 3+ years of combined experience in RTL design and DFT using Verilog/System Verilog Experience in ASIC...
Lugar: Chandler, AZ | 10/01/2026 18:01:56 PM | Salario: S/. No Especificado | Empresa: Intel
Senior Manager of SoC Virtual Platform Modeling, Annapurna Labs Machine Learning Accelerators, AWS
dive into technical issues and the codebase head-first - Work closely with architecture, RTL design, design verification...
Lugar: Cupertino, CA | 09/01/2026 21:01:38 PM | Salario: S/. No Especificado | Empresa: Amazon
Principal CAD Engineer
communication skills Ability to run the following tasks is a plus: RTL to gates, and gates-to-gates equivalence checking Chip...
Lugar: Santa Clara, CA | 08/01/2026 19:01:17 PM | Salario: S/. $146850 - 220000 per year | Empresa: Marvell
Physical Design Engineer
implementation of custom IP and SoC designs from RTL to GDS to create a design database that is ready for manufacturing. Conducts...
CPU Verification Engineer
closely with CPU architects, RTL developers, and physical design teams to enhance verification of sophisticated architectural...
Lugar: Austin, TX | 07/01/2026 02:01:05 AM | Salario: S/. No Especificado | Empresa: Intel
Director, SOC Design
SOC designs Lead the SOC design team by being hands-on with RTL coding, IP integration flows and drive quality... and security requirements Hands on experience with RTL Coding and methodologies, IP integration flows, design quality tools...
Lugar: Santa Clara, CA | 06/01/2026 18:01:40 PM | Salario: S/. No Especificado | Empresa: Marvell
DFT Design Engineer I, AWS Machine Learning Acceleration
Develop high coverage and cost effective DFT methodologies Perform RTL coding and Verification Participate in Silicon debug...
Lugar: Austin, TX | 31/12/2025 20:12:54 PM | Salario: S/. No Especificado | Empresa: Amazon
Senior Verification Engineer – AI SoC Development
work with SoC architects, microarchitects, full chip architects, RTL developers, postsilicon, and physical design teams...
Lugar: Folsom, CA | 24/12/2025 22:12:11 PM | Salario: S/. No Especificado | Empresa: Intel