Senior Staff Design Engineer

job responsibilities include RTL design, verification, synthesis, timing optimization, static timing check, CDC check, Lint check, power..., or similar field with 10+ years of experience on digital IC design. - Experience on RTL design using System Verilog, timing...

Lugar: Santa Clara, CA | 06/05/2026 21:05:37 PM | Salario: S/. $134390 - 201300 per year | Empresa: Marvell

Senior Staff SoC Design Engineer

Senior Staff SoC Design Engineer role focuses on SoC microarchitecture, RTL design, and full-chip integration for high... design flow — from architecture and specification through RTL development, integration, and design sign-off — in close...

Lugar: Santa Clara, CA | 06/05/2026 01:05:29 AM | Salario: S/. $134390 - 201300 per year | Empresa: Marvell

Senior Staff Emulation Engineer

across multiple teams. - Collaborate closely with Senior Emulation Engineers, RTL design, verification, and firmware teams... and subsystem issues across RTL, firmware, emulation platforms, and toolchain interactions. - Optimize emulation performance...

Lugar: Santa Clara, CA | 06/05/2026 00:05:48 AM | Salario: S/. $113920 - 170600 per year | Empresa: Marvell

Prinicipal Emulation Engineer

, software development, and system validation needs across multiple teams. - Collaborate closely with RTL design, verification... environment. - Debug complex SoC and subsystem issues across RTL, firmware, emulation platforms, and toolchain interactions...

Lugar: Santa Clara, CA | 05/05/2026 21:05:21 PM | Salario: S/. $158600 - 237600 per year | Empresa: Marvell

Principal Emulation Engineer

, software development, and system validation needs across multiple teams. - Collaborate closely with RTL design, verification... environment. - Debug complex SoC and subsystem issues across RTL, firmware, emulation platforms, and toolchain interactions...

Lugar: Santa Clara, CA | 05/05/2026 17:05:29 PM | Salario: S/. $158600 - 237600 per year | Empresa: Marvell

FPGA Intern (Fall 2026)

graduated from a four-year university, please apply to be an Associate Engineer. Role: RTL Development for FPGA targeted... converters, memories, MCUs Write software to interface and test RTL in hardware Collaborate closely with electrical...

Lugar: San Francisco, CA | 01/05/2026 02:05:39 AM | Salario: S/. $29 per hour | Empresa: Astrani

Sr Staff Digital Design Engineer

Expect Design, develop, implement, verify, and document micro-architecture and RTL for complex power management integrated... full design development cycle, end-to-end, from writing micro-architecture docs, RTL coding, specifications of timing...

Lugar: San Diego, CA | 01/05/2026 02:05:26 AM | Salario: S/. $135900 - 201130 per year | Empresa: Marvell

Director of SoC Design

of progress metrics. What We're Looking For BS degree or higher in EE or CE or CS 12-15+ years or more of RTL...

Lugar: San Diego, CA | 01/05/2026 02:05:23 AM | Salario: S/. No Especificado | Empresa: Marvell