Associate FPGA Engineer
for control and dataflow applications in small satellite avionics. Develop and verify VHDL RTL and top-level block diagram...
Lugar: State College, PA | 19/06/2026 17:06:19 PM | Salario: S/. No Especificado | Empresa: Airbus
Design Engineer, HBM DFT
readiness, test-mode sequencing, and MBIST validation for selected memories Collaborate with RTL, DV, PD, and Product/Test... sequential logic, clocks/resets, and timing concepts Experience or familiarity with synthesizable RTL such as SystemVerilog...
Lugar: Richardson, TX | 18/06/2026 20:06:40 PM | Salario: S/. No Especificado | Empresa: Micron
Post Silicon Engineer (eInfochips)
systems deployed in AWS data centers. You'll collaborate deeply with architecture, RTL design, design verification, firmware... validation engineers Executes complex test plans from RTL simulation and emulation environments through physical silicon...
Lugar: Austin, TX | 18/06/2026 19:06:13 PM | Salario: S/. No Especificado | Empresa: Arrow Electronics
Engineering Intern / Co-op
with FPGA / RTL (e.g. SystemVerilog, UVM, cocotb) Benefits Close mentorship and training End-to-end ownership of a scoped...
Lugar: Chicago, IL | 17/06/2026 17:06:52 PM | Salario: S/. $72800 - 114400 per year | Empresa: OceanComm, Inc.
Intern - Characterization and Support
electronics, RTL, Signal integrity, control systems Strong analytical and problem-solving skills The role is open for candidates...
Lugar: San Jose, CA | 13/06/2026 18:06:13 PM | Salario: S/. No Especificado | Empresa: Cadence Design Systems
Post-Silicon Systems Validation Engineer, Annapurna Labs
, RTL design, design verification, firmware, and software teams to ensure our next-generation AI/ML accelerators meet the... networks, ML HW architecture, and/or CI/CD - Familiarity with the validation lifecycle from RTL simulation (SystemVerilog/UVM...
Lugar: Austin, TX | 13/06/2026 00:06:50 AM | Salario: S/. No Especificado | Empresa: Amazon
Senior Staff Engineer, Digital IC Design
of experience. Proven experience in taping out complex SoCs and post silicon debug Strong RTL design skills in SystemVerilog.... Understanding of how front-end RTL decisions impact physical implementation and verification. Familiarity with industry standard...
Lugar: Santa Clara, CA | 12/06/2026 02:06:50 AM | Salario: S/. $134390 - 201300 per year | Empresa: Marvell
Senior Engineer, Design Verification
simulation of register-transfer level (RTL) and gate level designs using industry standard tools and processes. Collaborate...++ and Python scripting. RTL Design Debug. Functional Verification, Assertion-Based Verification, Constrained Random...
Lugar: Morrisville, NC | 12/06/2026 02:06:47 AM | Salario: S/. $97700 - 144410 per year | Empresa: Marvell
Staff Engineer, Design Verification
comprehensive functional verification against design specifications. Perform deep RTL debugging and root-cause analysis... and verification flows, with proficiency in RTL simulation and debugging. Capable of resolving complex technical issues independently...
Lugar: Westborough, MA | 12/06/2026 02:06:40 AM | Salario: S/. $128000 - 189370 per year | Empresa: Marvell
Senior Staff Engineer, Digital IC Design
fields with 3+ years of experience. Proven experience in taping out complex SoCs and post silicon debug Strong RTL design... constraints. Understanding of how front-end RTL decisions impact physical implementation and verification. Familiarity...
Lugar: Santa Clara, CA | 11/06/2026 23:06:41 PM | Salario: S/. $134390 - 201300 per year | Empresa: Marvell