Senior Design Engineer

, Register Transfer Level (RTL) design, synthesis/Lint/CDC/FEV and System on Chip (SOC) integration on different subsystems... specification development, RTL coding in Verilog/System Verilog and Clock Domain Crossing (CDC)/LINT closure. 4+ years of experience...

Lugar: Mountain View, CA | 09/12/2025 22:12:29 PM | Salario: S/. No Especificado | Empresa: Microsoft

ASIC Intern

. We are looking for interns across RTL Design, Physical Design, and Design Verification. You do not need experience across all three tracks.... Strength in one area (RTL, PD, or DV) is sufficient. As an RTL Intern at Etched, you will help design and implement the...

Lugar: San Jose, CA | 09/12/2025 22:12:09 PM | Salario: S/. No Especificado | Empresa: Etched