Senior Full Chip Physical Design Integration Lead

of cutting-edge technologies, transforming RTL to GDS databases ready for manufacturing. Your expertise in physical design flows..., multi-power plane design (MPP/UPF), and RTL to GDS workflows. Hands-on experience with scripting to automate design flows...

Lugar: United Kingdom - USA | 24/05/2026 20:05:23 PM | Salario: S/. No Especificado | Empresa: Intel

Director of Silicon Design for MEM/PCIE COE

customers — working at the intersection of architecture, RTL design, verification, firmware/software, and silicon validation.... What You Can Expect - Define and scales RTL development, drive reuse across IP and programs - Owns delivery of end-to-end PCIE...

Lugar: Santa Clara, CA | 22/05/2026 22:05:50 PM | Salario: S/. No Especificado | Empresa: Marvell

Senior AI SoC Design Engineer

and implement RTL for SoC blocks Collaborate with IP providers to integrate IPs into the SoC Collaborate with verification..., with experience in the following: RTL design, coding, and simulation using SystemVerilog. Microarchitecture and SoC architecture...

Lugar: Santa Clara, CA | 22/05/2026 22:05:25 PM | Salario: S/. No Especificado | Empresa: Intel

Senior AI SoC Design Engineer

and implement RTL for SoC blocks Collaborate with IP providers to integrate IPs into the SoC Collaborate with verification..., with experience in the following: RTL design, coding, and simulation using SystemVerilog. Microarchitecture and SoC architecture...

Lugar: Santa Clara, CA | 22/05/2026 21:05:05 PM | Salario: S/. No Especificado | Empresa: Intel

Senior Staff Design Engineer - PCIE/CXL Subsystem COE

customers — working at the intersection of architecture, RTL design, verification, firmware/software, and silicon validation.... What You Can Expect Own and drive PCIE/CXL subsystem micro-architecture definition, RTL implementation, and integration...

Lugar: Santa Clara, CA | 22/05/2026 19:05:17 PM | Salario: S/. $134390 - 201300 per year | Empresa: Marvell

Senior Staff Design Engineer - PCIE/CXL Subsystem COE

customers — working at the intersection of architecture, RTL design, verification, firmware/software, and silicon validation.... What You Can Expect Own and drive PCIE/CXL subsystem micro-architecture definition, RTL implementation, and integration...

Lugar: Irvine, CA | 22/05/2026 18:05:46 PM | Salario: S/. $135900 - 201130 per year | Empresa: Marvell