Senior Principal Engineer, Digital IC Design

Design Engineer, you will lead micro-architecture and RTL development and HW/SW co-design efforts working across multi... of the implemented RTL for LINT, CDC. Hands on experience in interpretive language such as Perl/Python. Proven track record...

Lugar: Santa Clara, CA | 25/04/2026 22:04:29 PM | Salario: S/. $158600 - 237600 per year | Empresa: Marvell

Senior Principal Engineer, Digital IC Design

communication ICs. The candidate will be involved in engineering implementation spec writing from system requirements, RTL design... and flow. RTL designs for various type of SerDes IPs ranging from 10Gbps to 224Gbps data-rates for different applications...

Lugar: Santa Clara, CA | 25/04/2026 17:04:12 PM | Salario: S/. No Especificado | Empresa: Marvell

Principal IC Digital Design - SoC Design/Micro-architecture

and RTL development and HW/SW co-design efforts working across multi-functional teams, in developing state-of-the-art designs.... Essential Duties and Responsibilities Own RTL design, implementation, and integration of complex blocks or subsystems Define...

Lugar: Santa Clara, CA | 23/04/2026 23:04:37 PM | Salario: S/. $158600 - 237600 per year | Empresa: Marvell

GPU Validation Engineer

architects, RTL developers, and physical design teams to enhance verification processes, meeting functional, performance...

Lugar: Folsom, CA | 21/04/2026 21:04:12 PM | Salario: S/. No Especificado | Empresa: Intel

Senior Emulation Engineer

across multiple teams. - Collaborate closely with RTL design, verification, and firmware teams to define requirements, develop... issues across RTL, firmware, emulation platforms, and toolchain interactions. - Optimize emulation performance, including...

Lugar: Santa Clara, CA | 16/04/2026 21:04:28 PM | Salario: S/. $158600 - 237600 per year | Empresa: Marvell

Senior Director of SoC Design

Looking For BS degree or higher in EE or CE or CS 15+ years or more of RTL and/or verification experience 5 + years of experience...

Lugar: San Diego, CA | 16/04/2026 20:04:26 PM | Salario: S/. No Especificado | Empresa: Marvell

Senior Staff Engineer, ASIC/VLSI Synthesis and Design

. Collaborate with Architecture, RTL, DFT, and Analog teams to understand the design requirements, analyze the timing complexities.... Strong understanding of ASIC design flows, from RTL to GDSII. Knowledge and hands-on experience with synthesis and STA methodologies...

Lugar: Irvine, CA | 16/04/2026 18:04:11 PM | Salario: S/. $135900 - 201130 per year | Empresa: Marvell