Principal Physical Design/Implementation Engineer

flows for Complex SubSystems Provide deep technical leadership in RTL-to-GDSII implementation, including synthesis, floor... team Work with DFT team and SOC team for DFT insertion and closing timing at SOC level Work with RTL team to close...

Lugar: Santa Clara, CA | 09/05/2026 20:05:36 PM | Salario: S/. $158600 - 237600 per year | Empresa: Marvell

Senior Staff Design Engineer

job responsibilities include RTL design, verification, synthesis, timing optimization, static timing check, CDC check, Lint check, power..., or similar field with 10+ years of experience on digital IC design. - Experience on RTL design using System Verilog, timing...

Lugar: Santa Clara, CA | 07/05/2026 00:05:18 AM | Salario: S/. $134390 - 201300 per year | Empresa: Marvell

CPU Core Physical Design Engineer

design implementation of custom CPU designs from RTL to GDS to create a design database that is ready for manufacturing...

Lugar: Folsom, CA | 06/05/2026 22:05:39 PM | Salario: S/. No Especificado | Empresa: Intel