CPU Core Logic Designer

transfer level (RTL) coding, and simulation for a CPU required to generate cell libraries, functional units, and the CPU IP... features of the CPU being designed. Applies various strategies, tools, and methods to write RTL and optimize logic to qualify...

Lugar: Folsom, CA | 12/12/2025 19:12:13 PM | Salario: S/. No Especificado | Empresa: Intel

Entry Level Hardware Test Engineer

areas: Microprocessor/ASIC Design Skills: VHDL, Verilog, RTL, SPICE, TCL, UVM, verification, and testing Computer...

Lugar: USA | 12/12/2025 18:12:45 PM | Salario: S/. No Especificado | Empresa: IBM

Entry Level Hardware Developer 2026

process, such as: Logic (RTL) design and verification, physical design, and analog/IO design Electronic design automation..., Verilog, RTL, SPICE, TCL, UVM, verification, and testing Computer Architecture coursework: VLSI Design, Microprocessors...

Lugar: USA | 11/12/2025 18:12:17 PM | Salario: S/. No Especificado | Empresa: IBM

Entry Level Hardware Developer

(C/C++/C#, Python, or Java), hardware description languages (RTL/VHDL/Verilog), and circuit simulation tools (SPICE..., Verilog, RTL, SPICE, TCL, UVM, verification, and testing Computer Architecture coursework: VLSI Design, Microprocessors...

Lugar: USA | 11/12/2025 18:12:21 PM | Salario: S/. No Especificado | Empresa: IBM

Senior FPGA Development Engineer, Bespoke Solutions

for each government agency for which they perform AWS work. 10012 Key job responsibilities - Develop custom RTL and integrate... with custom hardware. You will debug RTL in simulation, synthesize and implement ensuring it meets timing and performance...

Lugar: Arlington, VA | 10/12/2025 20:12:21 PM | Salario: S/. $159200 - 215300 per year | Empresa: Amazon

ASIC Intern

. We are looking for interns across RTL Design, Physical Design, and Design Verification. You do not need experience across all three tracks.... Strength in one area (RTL, PD, or DV) is sufficient. As an RTL Intern at Etched, you will help design and implement the...

Lugar: San Jose, CA | 09/12/2025 21:12:52 PM | Salario: S/. No Especificado | Empresa: Etched

Bell Labs Platform&ASIC Research Intern

DSPs Advanced RTL development skills and fluent in HDL (Verilog, SystemVerilog, and VHDL) and/or HLS (High-level Synthesis... in gate or RTL-level design optimization, timing closure analysis, and/or mixed-signal circuit design About Us: Advancing...

Lugar: Murray Hill, NJ | 05/12/2025 23:12:24 PM | Salario: S/. No Especificado | Empresa: Nokia