Principal Engineer, ASIC/VLSI Synthesis and Design

and validate timing constraints for intricate SoC designs. Collaborate with Architecture, RTL, DFT, and Analog teams... experience in ASIC implementation and synthesis. Strong understanding of ASIC design flows, from RTL to GDSII. Knowledge...

Lugar: San Diego, CA | 29/05/2026 00:05:08 AM | Salario: S/. $160400 - 237320 per year | Empresa: Marvell

Senior Staff Engineer, ASIC/VLSI Synthesis and Design

and validate timing constraints for intricate SoC designs. Collaborate with Architecture, RTL, DFT, and Analog teams... experience in ASIC implementation and synthesis. Strong understanding of ASIC design flows, from RTL to GDSII. Knowledge...

Lugar: San Diego, CA | 28/05/2026 21:05:50 PM | Salario: S/. $135900 - 201130 per year | Empresa: Marvell

Staff Engineer, ASIC/VLSI Synthesis and Design

and validate timing constraints for intricate SoC designs. Collaborate with Architecture, RTL, DFT, and Analog teams... experience in ASIC implementation and synthesis. Strong understanding of ASIC design flows, from RTL to GDSII. Knowledge...

Lugar: San Diego, CA | 28/05/2026 18:05:31 PM | Salario: S/. $115200 - 170390 per year | Empresa: Marvell

FPGA Engineer, LEO KMM FPGA

you will: Have ownership of one or more FPGA bitstreams. - Create and release FPGAs through the development phases of uArchitecture-RTL Design...

Lugar: San Diego, CA | 27/05/2026 23:05:46 PM | Salario: S/. No Especificado | Empresa: Amazon

Physical Design Engineer for Core IP

of custom CPU designs from RTL to GDS to create a design database that is ready for manufacturing. Conducts all aspects of the... of Static Timing Analysis, Noise analysis, and reliability verification techniques Strong knowledge of RTL to GDS methodologies...

Lugar: Hillsboro, OR | 27/05/2026 21:05:38 PM | Salario: S/. No Especificado | Empresa: Intel