MTS Silicon Design Engineer

;SOC Full Chip Floor Planning;ASIC Design and RTL design and coding;Full Chip timing closure, including signal... integrity, RC extraction, and clock tree synthesis;Chip design utilizing CAD tools (Synopsys and Cadence);RTL and Power...

Lugar: Santa Clara, CA | 09/05/2026 19:05:38 PM | Salario: S/. No Especificado | Empresa: Advanced Micro Devices

Silicon Design Engineer

following: Developing synthesizable RTL (SystemVerilog / Verilog) for complex digital blocks;Implementing control logic..., datapaths, state machines, and protocol engines;Ensuring RTL adheres to coding guidelines, clocking/reset strategies, and low...

Lugar: San Jose, CA | 09/05/2026 18:05:06 PM | Salario: S/. No Especificado | Empresa: Advanced Micro Devices

Senior Staff Design Engineer

job responsibilities include RTL design, verification, synthesis, timing optimization, static timing check, CDC check, Lint check, power..., or similar field with 10+ years of experience on digital IC design. - Experience on RTL design using System Verilog, timing...

Lugar: Santa Clara, CA | 07/05/2026 01:05:11 AM | Salario: S/. $134390 - 201300 per year | Empresa: Marvell