CPU Formal Verification Engineer

Intel's leadership in the semiconductor industry. This is a unique opportunity to collaborate closely with architects, RTL... to implement verification plans and resolve failing tests using corrective measures. Collaborate with architects, RTL developers...

Lugar: Hillsboro, OR | 21/05/2026 18:05:47 PM | Salario: S/. $105650 - 149150 per year | Empresa: Intel

Senior Staff Emulation Engineer

across multiple teams. - Collaborate closely with Senior Emulation Engineers, RTL design, verification, and firmware teams... and subsystem issues across RTL, firmware, emulation platforms, and toolchain interactions. - Optimize emulation performance...

Lugar: Santa Clara, CA | 21/05/2026 02:05:00 AM | Salario: S/. $113920 - 170600 per year | Empresa: Marvell

Prinicipal Emulation Engineer

, software development, and system validation needs across multiple teams. - Collaborate closely with RTL design, verification... environment. - Debug complex SoC and subsystem issues across RTL, firmware, emulation platforms, and toolchain interactions...

Lugar: Santa Clara, CA | 20/05/2026 23:05:35 PM | Salario: S/. $158600 - 237600 per year | Empresa: Marvell

Prinicipal Emulation Engineer

, software development, and system validation needs across multiple teams. - Collaborate closely with RTL design, verification... environment. - Debug complex SoC and subsystem issues across RTL, firmware, emulation platforms, and toolchain interactions...

Lugar: Santa Clara, CA | 20/05/2026 21:05:03 PM | Salario: S/. $158600 - 237600 per year | Empresa: Marvell

SoC Design Engineer

. You will be responsible for developing high-quality logic designs, coding register transfer level (RTL) models, and performing thorough... Develop logic designs and RTL code for SoC designs, ensuring alignment with architectural and microarchitectural...

Lugar: Austin, TX | 17/05/2026 18:05:29 PM | Salario: S/. No Especificado | Empresa: Intel

Front End CAD Principal Engineer

. Proficiency in Verilog / System Verilog Design and Verification. Experience in RTL linting tools, including clock domain crossing... (CDC). Experience in git revision control. Knowledge in Equivalence Checking for both RTL to gates and gates to gates...

Lugar: Santa Clara, CA | 15/05/2026 22:05:57 PM | Salario: S/. $150680 - 225700 per year | Empresa: Marvell