IP Design Verification Engineer

for validating portions of a complex microarchitecture using written specs, RTL code and other tests as a guide. Learning... debug of failures on silicon and developing new testing strategies to detect these failures on RTL models. Engaging with IP...

Lugar: Hillsboro, OR | 20/03/2026 02:03:35 AM | Salario: S/. $122440 - 172860 per year | Empresa: Intel

FPGA Electrical Engineer

, create specification documents. – Develop RTL designs using SystemVerilog, with emphasis on DSP and digital communication... of experience in SystemVerilog, Verilog, or VHDL RTL design. – 2+ years of experience in scripting and programming languages in two...

Lugar: Linthicum Heights, MD | 20/03/2026 00:03:39 AM | Salario: S/. No Especificado | Empresa: Next Step Systems

Lead CPU Design Engineer

Responsibilities: Develop the logic design and register transfer level (RTL) coding for CPU features. Perform simulation... and methods. Review and contribute to verification plans to ensure correctness of CPU design features. Resolve failing RTL tests...

Lugar: Phoenix, AZ | 19/03/2026 20:03:46 PM | Salario: S/. No Especificado | Empresa: Intel

Senior Staff Digital Design Engineer

blocks.  Own RTL development for assigned blocks, delivering high‑quality, synthesizable SystemVerilog RTL that meets... ASIC design, including micro‑architecture development, RTL implementation (SystemVerilog preferred), and integration...

Lugar: Irvine, CA | 19/03/2026 19:03:17 PM | Salario: S/. $135900 - 201130 per year | Empresa: Marvell

Senior Emulation Engineer

, and system validation needs across multiple teams. - Collaborate closely with RTL design, verification, and firmware teams.... - Debug complex SoC and subsystem issues across RTL, firmware, emulation platforms, and toolchain interactions. - Optimize...

Lugar: Santa Clara, CA | 17/03/2026 20:03:18 PM | Salario: S/. $134390 - 201300 per year | Empresa: Marvell

PD Intern

. You will assist in developing and running Physical Design flows to synthesize blocks, automate final design checks, and advise RTL... with transformer models and machine learning Familiarity with numerical representations and functions (RTL) Familiarity...

Lugar: San Jose, CA | 13/03/2026 01:03:44 AM | Salario: S/. No Especificado | Empresa: Etched