Digital IC Design Engineer Intern

, your responsibilities will include: Micro-architecture design and RTL implementation of: Low-power digital signal processors Low... in SystemVerilog, C/C++, Python Experience working on complex digital systems from architecture, microarchitecture, and RTL, using...

Lugar: Fremont, CA | 29/10/2025 03:10:59 AM | Salario: S/. $35 per hour | Empresa: Neuralink

FPGA Intern (Winter 2026)

from a four-year university, please apply to be an Associate Engineer. Role: RTL Development for FPGA targeted applications..., memories, MCUs Write software to interface and test RTL in hardware Collaborate closely with electrical and software...

Lugar: California | 17/10/2025 02:10:14 AM | Salario: S/. $29 per hour | Empresa: Astrani