Pre-Silicon Verification Engineer

in technical reviews with design teams Collaborate cross-functionally with architects, RTL developers, and analog design teams...-functional teams including architects, RTL developers, and analog design teams Strong attention to detail when documenting test...

Lugar: Hillsboro, OR | 11/10/2026 17:10:04 PM | Salario: S/. $122440 - 172860 per year | Empresa: Intel

FPGA System Design Engineer

Responsibilities Design, develop, and implement FPGA-based solutions using RTL, DSP Builder, and embedded processor technologies...

Lugar: San Jose, CA | 15/08/2026 01:08:40 AM | Salario: S/. $118900 - 172200 per year | Empresa: Altera

FPGA Engineer

(GPPs) and microcontrollers. Position Responsibilities · Develop and maintain general-purpose and mission specific RTL...

Lugar: Albuquerque, NM | 18/09/2026 23:09:35 PM | Salario: S/. $112500 - 171750 per year | Empresa: AeroVironment

FPGA Engineer

(GPPs) and microcontrollers. Position Responsibilities · Develop and maintain general-purpose and mission specific RTL...

Lugar: Albuquerque, NM | 18/09/2026 22:09:21 PM | Salario: S/. $112500 - 171750 per year | Empresa: AeroVironment

Director, Corporate Benefits

in some 50 countries around the world. It includes the entertainment group RTL Group, the trade book publisher Penguin Random...

Lugar: New York City, NY | 24/09/2026 23:09:30 PM | Salario: S/. $150000 - 170000 per year

Multi-Asset Warehouse Financing Middle Office VP

. Product exposure to include RTL, NQM, MSR, NPL/RPL, SBC, SFR. Warehouse Lending responsibilities to include daily trade flow... with client specific as well as trade specific documentation Exposure to various mortgage products including RTL, SBC, NQM, NPL...

Lugar: New York City, NY | 10/09/2026 18:09:32 PM | Salario: S/. $150000 - 170000 per year | Empresa: Nomura

FPGA Design Engineer

system bring-up, and supporting production deployment. Responsibilities: RTL Development & Verification: Develop..., integrate, simulate, and verify Verilog and SystemVerilog RTL code, including custom testbench creation. FPGA Flow...

Lugar: Santa Clara, CA | 10/10/2026 22:10:26 PM | Salario: S/. $110000 - 170000 per year | Empresa: Arista Networks

FPGA Design Engineer

system bring-up, and supporting production deployment. Responsibilities: RTL Development & Verification: Develop..., integrate, simulate, and verify Verilog and SystemVerilog RTL code, including custom testbench creation. FPGA Flow...

Lugar: Roseville, CA | 10/10/2026 17:10:20 PM | Salario: S/. $110000 - 170000 per year | Empresa: Arista Networks

FPGA Design Engineer

system bring-up, and supporting production deployment. Responsibilities: RTL Development & Verification: Develop..., integrate, simulate, and verify Verilog and SystemVerilog RTL code, including custom testbench creation. FPGA Flow...

Lugar: Roseville, CA | 10/10/2026 17:10:29 PM | Salario: S/. $110000 - 170000 per year | Empresa: Arista Networks