Design Verification Engineer - FPGA/ASIC

, you will be part of a verification team responsible for the full cycle of RTL verification for FPGA and ASIC designs. Over the span...

Lugar: USA | 29/10/2024 21:10:22 PM | Salario: S/. $102000 - 145000 per year | Empresa: Viasat

Sr ASIC Modem design Engineer (RTL,Wireless ), Project Kuiper

specification to RTL to optimizing timing / power to chip level validation. · Develop solutions optimizing customer experience... and systems in RTL. · Ability to convert DSP algorithms into RTL code and optimize for performance, power, and area. PREFERRED...

Lugar: San Diego, CA | 08/01/2025 03:01:44 AM | Salario: S/. $143300 per year | Empresa: Amazon