Digital IC Design Intern, MS - Summer 2027

design efforts Develop and verify detailed, high-performance RTL design blocks and apply the digital design...-on experience with RTL design and a firm understanding on how it integrates into the overall ASIC design flow Strong analysis...

Lugar: Santa Clara, CA | 22/09/2026 17:09:12 PM | Salario: S/. $35 - 70 per hour | Empresa: Marvell

Physical Design Engineer Intern, MS - Summer 2027

fixes for design violations using CAD tools Collaborate with RTL, Synthesis, and other Design teams to resolve congestion... architecture, RTL synthesis, Verilog or SystemVerilog, place and route, static timing analysis, digital systems...

Lugar: Santa Clara, CA | 05/09/2026 18:09:50 PM | Salario: S/. $34 - 68 per hour | Empresa: Marvell

FPGA Engineer

, and deployment of FPGA-based products. This position is open to candidates with 7-10 years of experience, focusing on RTL design...-based products with a focus on RTL design, FPGA development, and simulation. Collaborate with hardware, embedded software...

Lugar: Newtown, PA | 27/10/2026 20:10:20 PM | Salario: S/. $55 - 67 per hour | Empresa: Actalent

FPGA Engineer

, and deployment of FPGA-based products. This position is open to candidates with 7-10 years of experience, focusing on RTL design...-based products with a focus on RTL design, FPGA development, and simulation. Collaborate with hardware, embedded software...

Lugar: Newtown, PA | 23/10/2026 02:10:26 AM | Salario: S/. $55 - 67 per hour | Empresa: Actalent

Digital IC Design Intern, BS - Summer 2027

design efforts Develop and verify detailed, high-performance RTL design blocks and apply the digital design...-on experience with RTL design and a firm understanding on how it integrates into the overall ASIC design flow Strong analysis...

Lugar: Santa Clara, CA | 22/09/2026 17:09:54 PM | Salario: S/. $30 - 59 per hour | Empresa: Marvell

Physical Design Engineer Intern, BS - Summer 2027

fixes for design violations using CAD tools Collaborate with RTL, Synthesis, and other Design teams to resolve congestion... architecture, RTL synthesis, Verilog or SystemVerilog, place and route, static timing analysis, digital systems...

Lugar: Santa Clara, CA | 05/09/2026 23:09:02 PM | Salario: S/. $29 - 57 per hour | Empresa: Marvell