design efforts Develop and verify detailed, high-performance RTL design blocks and apply the digital design...-on experience with RTL design and a firm understanding on how it integrates into the overall ASIC design flow Strong analysis...
and write & debug a testbench Hands-on experience with RTL integration and bring-up system Experience with debugging complex...
fixes for design violations using CAD tools Collaborate with RTL, Synthesis, and other Design teams to resolve congestion... architecture, RTL synthesis, Verilog or SystemVerilog, place and route, static timing analysis, digital systems...
, and deployment of FPGA-based products. This position is open to candidates with 7-10 years of experience, focusing on RTL design...-based products with a focus on RTL design, FPGA development, and simulation. Collaborate with hardware, embedded software...
Lugar:
Newtown, PA | 27/10/2026 20:10:20 PM | Salario: S/. $55 - 67 per hour | Empresa:
Actalent, and deployment of FPGA-based products. This position is open to candidates with 7-10 years of experience, focusing on RTL design...-based products with a focus on RTL design, FPGA development, and simulation. Collaborate with hardware, embedded software...
Lugar:
Newtown, PA | 23/10/2026 02:10:26 AM | Salario: S/. $55 - 67 per hour | Empresa:
Actalent Units to conduct product security testing on selected products at RTL design phase using specialized methods/tools. Learn... in testing and debug in pre-silicon environment. Good Verilog, System Verilog programming skills to understand RTL design. Good...
Lugar:
Chandler, AZ | 25/09/2026 02:09:56 AM | Salario: S/. $30 - 59 per hour | Empresa:
Marvell design efforts Develop and verify detailed, high-performance RTL design blocks and apply the digital design...-on experience with RTL design and a firm understanding on how it integrates into the overall ASIC design flow Strong analysis...
and write & debug a testbench Hands-on experience with RTL integration and bring-up system Experience with debugging complex...
fixes for design violations using CAD tools Collaborate with RTL, Synthesis, and other Design teams to resolve congestion... architecture, RTL synthesis, Verilog or SystemVerilog, place and route, static timing analysis, digital systems...
and RTL designs using Vivado. Capture and analyze screenshots with more than 2.5 megapixels using either a high-resolution...