Engineering Intern - ASIC DFT (Spring 2027 Co-Op)

setup using Post -DFT RTL/Netlist. Run simulation using the test list or patterns. Memory Built-in Self test[MBIST... Engineering, or Computer Science Digital Logic design RTL Coding like Verilog /VHDL/System Verilog TCL/Python Scripting...

Lugar: Palo Alto, CA | 01/10/2026 21:10:41 PM | Salario: S/. $45 - 51 per hour | Empresa: Rivian