Design Verification Engineer - SoC

, deep technical ability, and the drive to tackle complex verification challenges. You will collaborate with architects, RTL... responsibilities Work closely with architects and RTL designers on verifying the performance features of the design and correlating...

Lugar: Austin, TX | 02/11/2026 23:11:35 PM | Salario: S/. No Especificado | Empresa: Etched

ASIC Architect

and interface definitions for compute blocks and subsystems Collaborate with RTL, verification, physical design, and software... also have experience with AI/ML accelerator architectures and dataflow optimization RTL design and verification (Verilog/SystemVerilog...

Lugar: San Jose, CA | 02/11/2026 23:11:16 PM | Salario: S/. No Especificado | Empresa: Etched

Emulation Engineer, Hardware Prototyping (HAPS)

is redefining the infrastructure layer for the fastest growing industry in history. What you'll do Own HAPS bring-up. Take RTL... are your customers. You'll help them get running, triage their failures, and figure out whether the bug is theirs, the RTL's, or the...

Lugar: San Jose, CA | 02/11/2026 22:11:58 PM | Salario: S/. No Especificado | Empresa: Etched

Post-Silicon Validation Engineer

. Perform deep-dive debug of silicon issues across RTL, firmware, and system levels. Collaborate closely with design... and subsystems. Partner with RTL, DFT, ATE, firmware, and system architecture teams to ensure smooth transition from pre-silicon...

Lugar: San Jose, CA | 02/11/2026 22:11:02 PM | Salario: S/. No Especificado | Empresa: Etched

Design Verification Engineer - Internal IP

ability, and the drive to tackle complex verification challenges. You will collaborate with architects, RTL designers, and SW... bottlenecks. Debug complex datapath and protocol issues in RTL and testbench environments. Work closely with architects...

Lugar: Austin, TX | 02/11/2026 22:11:54 PM | Salario: S/. No Especificado | Empresa: Etched

Design Verification Engineer - SoC

, deep technical ability, and the drive to tackle complex verification challenges. You will collaborate with architects, RTL... responsibilities Work closely with architects and RTL designers on verifying the performance features of the design and correlating...

Lugar: San Jose, CA | 02/11/2026 22:11:01 PM | Salario: S/. No Especificado | Empresa: Etched

Physical Design Engineer - Block Level, Subsystem Implementation

from synthesis through GDSII sign-off. You will drive Block-level & Subsystem PPA Optimization, and collaborate closely with RTL... budgets for clean hierarchical integration of your blocks into the top level. Collaborate with RTL Designers and provide...

Lugar: Austin, TX | 02/11/2026 21:11:26 PM | Salario: S/. No Especificado | Empresa: Etched

Physical Design Engineer - Flow & Methodologies

Responsibilities Architect, build, and maintain our automated RTL-to-GDSII flow, from synthesis through place and route to signoff... if you have 5-10+ years of previous experience with PD or PD methodology/CAD Experience building and owning automated RTL-to-GDSII...

Lugar: San Jose, CA | 02/11/2026 21:11:58 PM | Salario: S/. No Especificado | Empresa: Etched